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The Promise of Open Source EDA Software
Author’s Note: If you want to watch the full video, it is below
I managed to speak with friend of channel Matt Venn of the “From Zero to ASIC Course” (go check it out) about the state of the open source hardware ecosystem. It is really impressive to look at the progress open source has made in the past few years. There are times when nobody would consider using Linux or GCC in production items. Now they are core parts of the infrastructure.
I don’t know if open source hardware will ever get to that same spot, but right now there are certain specific use cases when open source EDA tools are finding their ways into production hardware.
For now, the biggest issue that open source addresses has to do with access. With open source, someone like Matt can use and teach tools in his course that anyone can go and download. They don’t have to first sign up and purchase a seat from a big company. It’s such a game changer in terms of helping to educate the community and more.
In 2018, DARPA announced that the United States will invest $100 million in new open source tools and silicon blocks to create SOCs and circuit boards. The goal is to try and bend the cost curve of making modern semiconductor silicon.
While an open source EDA software community has been around for several decades, the increasing difficulty of fabbing at the leading edge has caused it to gradually fall behind the commercial industry.
But now, open source hardware innovations like RISC-V have been casting a lot of light onto the open source EDA space as well. In this fun little video, we are going to take a look at the ecosystem as it is today.
Why Open Source?
So why should we care about open source EDA? Over the past few videos, I have talked about some major technical challenges in the semiconductor design industry. Verification and EDA productivity, for instance.
Now it is time to talk about one more big semiconductor design blocker, and that is cost and stagnancy. Designing a semiconductor - not even the latest 5nm ones - is difficult and expensive. And part of the reason why has to do with IP licenses.
For instance, the Instruction Set Architecture or ISA. The most common ISAs are controlled by companies like Intel and ARM. Developer unwillingness to pay the required licensing costs has contributed to the rise of open source hardware projects like RISC-V.
EDA tools have their own costs as well. There are three major EDA companies. They invest a lot into their work, spending a quarter of their revenues on R&D, so they obviously deserve their high fees.
But these companies' primary audiences are major enterprise clients like Nvidia, Apple, and Qualcomm.
The enterprise EDA industry is not all that suited to support the smaller guys. If you're a small team trying to make a $10 IOT chip or have specific design requirements like reliability or security, things get complicated.
The Deeper Costs of Licensing
But it's more than just the money and the support. Proprietary IP licenses cut into the value of sharing.
A lot of research gets published about things people have done in the industry. And this research can potentially be really helpful to others in the industry.
For instance, Google TensorFlow - an open source library that helps you develop and train machine learning models. After it went open source, TensorFlow has been adopted by both research and corporate teams.
The fact that these two types of teams use the same framework makes commercialization easier. Research results can be more easily shared and replicated by other members of the community. Contributions and improvements can flow throughout both worlds.
I remember downloading data sets and running TensorFlow on my computer to try to do computer vision tutorials. I was so excited that I got to be able to give this industry standard technology a test-drive.
This is much harder when the research and commercial communities are dependent on proprietary IPs that cost a lot of money or require an NDA. Students, teachers, enthusiasts, and other niche developers do not necessarily have access to this type of stuff. Furthermore, this reduces the number of people proficient with these tools, creating shortages.
How can they learn and create on top of the work others have done before them? This is a big blocker in the hardware community. Open source helps bring back some of that interoperability and collaboration.
An Overview of Open Source EDA: The Early Years
Open source EDA tools have existed since the 1980s with some pre-dating even Linux by a few years. A few in particular are still used to to this day. I want to take some time to cover a few.
SPICE is a general purpose circuit simulation program. It dates back to the early 1970s at my alma mater UC Berkeley, where it has been used to teach a generation of chip designers.
Practical, reliable, easy to use, and most of all, free, the software became so popular that its name became a verb: "Let's SPICE that and see if it works!"
Another popular software is Magic, which is an interactive system for creating and modifying VLSI circuit layouts.
Based on the Mead-Conway style of design, it uses a simple set of rules to let you design basic cells in a large, hierarchical structure.
I talked a little bit about Mead-Conway in a previous video which might be fun for you to check out if that interests you.
The last software I want to talk about is VIS or Verification Interacting with Synthesis. In other words, it is a tool for automatic formal verification.
I talked about verification in a previous video, which I hope can be more informative about what that is.
So tools do indeed exist within the open source EDA ecosystem. And some very smart people have been able to bundle these tools together to create end-to-end software flows.
For instance, Qflow - which is a chain that wants to take you from verilog source to physical layout, ready for a fabrication process.
There is no doubt all of these are useful. A lot of it is still being used to this day. But the semiconductor ecosystem has dramatically grown over the years, and the open source EDA community has fallen far behind.
Overview: Recent Events
DARPA wants to shake things up a bit and scratch a different itch from that of the commercial EDA industry. The big semiconductor fabless companies have huge engineering staffs at their disposal - supposedly Apple has 3,000 people just building a modem - with the goal of making the most hyper-optimized thing possible.
As a result, a lot of what goes into chip design is manual effort - doing the logic, floorplanning, routing, so on. That’s what’s necessary to get the absolute best performance, and you have the money and manpower to make it happen.
But what if you don’t? Whats there for you? So in June 2018, DARPA funded and launched OpenROAD.
OpenROAD wants to make it easy to go from RTL - so like verilog - to a final manufacturable layout for SOCs and circuit boards in 24 hours, no additional people needed.
Since the 2018 launch, the project has progressed quickly - with the 1.0 integrating some twenty tools into a single app.
For instance, one tool is called RePlAce, which is a floorplanner. I touched on the topic in a previous video where I talked about Google's machine learning floor planner.
The tool has seen a few heartening successes including tapeouts for a 12 nanometer SOC and passing verification checks for a TSMC 65 nanometer low power and GlobalFoundries 12 nanometer low power process. It even has a graphical user interface, or GUI.
I want to talk about two other projects. The first of which is Chisel.
This is an alternative to languages like Verilog and VHDL. But it blends in certain software architectures, since it is based on Scala. I personally like the way it reads. Feels more modern.
It is notable for being the HDL used in Berkeley's Rocket Chip, a RISC-V chip generator.
Lastly, one very worthy project that hits at a very important pain point is OpenRAM. Every system on a chip has a memory component embedded within, called Static Random Access Memory or SRAM.
Memory designs are a big deal in chip design, and not having an advanced standard that every researcher can use hinders research. And at more advanced nodes, memory gets to be a particularly tricky part of the chip to design. So what these guys are doing is pretty valuable in my opinion.
The PDK Roadblock
There remain a few roadblocks in the open source hardware system beyond the EDA world. The most significant of which is the Process Design Kit or PDK.
A PDK is a set of design rules and physical limitations packaged with simulators, third-party pre-designed IP libraries, design rule checkers, and other design tools. It is provided to the fabless design companies by a foundry like TSMC or GlobalFoundries.
The PDK and EDA software are very tightly coupled. Since the foundry has to create, maintain and provide support for this to EDA software vendors, the foundry is incentivized to only work with a few companies to keep it simple.
The lack of an integrated PDK has left many open-source EDA efforts somewhat half-hearted. The foundry is doing the fabbing, after all. Their contribution is essential in order for the EDA software to be actually commercially usable.
However, the PDK is a reflection of how the foundry does its work. Only TSMC's most important customers like Apple get to see the N5 or N3 PDK. Even for older nodes, TSMC will make you sign an NDA. So no way are they ever open sourcing it.
But if a foundry isn’t trying to compete at the leading edge, you can make a business case for open-sourcing a PDK for a way older, less sophisticated node.
Skywater Technologies, a company I profiled in a previous video, is taking this exact pathway. Recently, they partnered with Google to launch a PDK for their 130 nanometer node - freely available on Github. This has allowed others to scrutinize and improve the PDK, and such things have already happened.
Side note. Recently Google has been doing a lot for open source hardware design. I know they have their own incentives for doing so, but it’s still pretty cool.
The announcement was streamed live on YouTube in June 2020 and received 10,000 views in its first week. It now has about 23,700 views - which is not too shabby - and reflects the growing popularity of the space.
Other projects of this type include the academic-oriented FreePDK. And OpenROAD also recently open sourced a PDK of its own - ASAP7, which is a research PDK for the 7 nanometer FinFet process node. However, these are more for academia and shouldn't be used for commercial purposes.
Open source has accomplished some really amazing things over in the software world. Some frameworks like Rails are as good as anything you can pay for. So I think there might be a temptation to see open source EDA as something like the same: As good as anything you pay for, but for free. A pressure on the commercial EDA giants.
I don’t think that’s going to be the case. Open source EDA will never be something that is top of the line - the phrase the OpenROAD foundation uses is "ultimate quality of results". Market leading semiconductor design is so optimized that trying for that is a fool’s errand. Rather, what the community is looking to achieve is what the organization calls "ultimate ease of use".
Not every chip needs to be a five-nanometer monster. What they want to do is to make it easier for everyone to design, make, and contribute to open source hardware. To give teams all around the world the chance to make cool stuff. And I think that’s way more exciting.