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The 3-D Transistor Transition
Starting in 2011, Intel and the rest of the leading edge semiconductor industry made a remarkable technical transition.
For the first time, the industry began producing transistors in three dimensions - largely referred to as the Fin Field-effect Transistor, or FinFET.
It was a move over ten years in the making. Why was it necessary? For this video, let us look back at this historic industrial move.
For decades, the semiconductor industry's building block was the Metal-Oxide Semiconductor Field Effect Transistor or MOSFET.
This transistor is very common in digital circuits like inverters, NAND gates, and SRAM cells.
It is made up of a gate sitting on top of a channel connecting a source and a drain.
The source and the drain are basically just regions of silicon doped with the atoms of other elements to donate or receive electrons.
The gate sits on top of the channel - keep that in mind. There is also a thin insulating layer between the two - usually made from silicon oxide. The gate does not cut through the channel itself.
With the exception of this gate and its insulating layer, the whole thing is flat, or planar.
This gate can be made to allow electrons to move along the channel from the source to the drain. Switch the gate off, and the flow of electrons stops. Or at least it is supposed to ... when everything is going right.
For the first few decades of the semiconductor industry, new process nodes delivered performance, power, and area gains simply by shrinking the transistor's physical dimensions and cramming more of them onto a chip.
This was called classical scaling. The integrated circuits worked better because the electric signals had less distance to travel between each transistor.
As laid out in 1974 by IBM researcher Robert Dennard, a secondary but equally important benefit was that those smaller transistors also used less power.
Moore's Law pushed the semiconductor industry to reduce their transistors' linear dimensions in half every 3 years. In the 1980s, dimensions fell under 1 micron for the first time.
Around that time, people started to notice that their transistors started to act a bit funny.
As the transistor's physical dimensions shrinks, the source and the drain gets closer and closer together. The insulating layer between the gate and channel gets thinner - 1.2 nanometers at one point or 5 atoms wide. And the channel itself gets thinner, as well.
With that, the gate's control over the current's flow from the source to the drain gets weaker.
And what basically then happens is that the current "dives under the gate" as it goes from the source to the drain.
Like a rabbit burrowing into a farmer's vegetable patch, current can now sneak from the source to the drain even if the gate is closed. It can travel through the part of the channel furthest away from the gate, or in some circumstances even through the silicon substrate itself.
This is called the "short-channel effect" and by the mid-1990s - the 350 nanometer process node - it was becoming a serious industrial concern.
In addition to unpredictable behaviors, there are serious issues with power consumption. This leakage meant that these smaller transistors did not follow Dennard scaling.
The way things were going, transistors would consume as much energy in their "off" state as they did during their "on" state. This came at a time when consumer electronics started to get more portable, leading to higher demands on power efficiency.
Researchers soon realized that they were fighting a losing battle. The classical MOSFET structure had a final end point - a practical, final size limit at about the 20 nanometer mark. Nobody saw a path to extend this final runway.
In 1996, with the leading edge at 250 nanometers, DARPA became aware that the industry did not have a long term plan beyond the year 2002 - 5 years away. They called for proposals of research on sub-25 nanometer devices, titled the 25-nm Switch.
The 25nm Switch
DARPA received 10-12 proposals from IBM, AT&T, and of course Stanford. However, all of these were mere extensions of the original MOSFET structure. That was not what DARPA wanted. They wanted something ambitious and feasible.
The winning selection came from a team at the University of California, Berkeley, led by Professor Hu Chenming (胡正明).
Professor Hu joined Berkeley in 1976. Early on, he studied energy topics like hybrid cars. But government funding on that soon dried up after the Reagan administration came into power and he pivoted to semiconductor research.
In 1982, Hu took a sabbatical to work at National Semiconductor. There, he had the chance to see the coming end of the planar transistor from the front lines.
After hearing about the DARPA call for proposals from a fellow Berkeley faculty member, he gathered a crew and came up with the final submitted proposal over the span of a week.
The proposal - titled “Novel Fabrication, Device Structures, and the Physics of 25 nm FETs for Terabit-Scale Electronics” - brought up two ideas, both of which focused on the idea of giving the gate better control over the channel itself.
The first is called fully depleted silicon-on-insulator or FD-SOI. If electrons are inappropriately traveling using the silicon substrate, then we add a new layer of insulation on top of the silicon substrate to prevent that from happening.
FDSOI became moderately successful. The industry has adopted it for specific uses like analog or power electronics. The second idea - which Professor Hu sketched up during a long flight - was the FinFET.
The FinFET Rises
As I mentioned earlier, the focus is to allow the gate to have better control over the channel.
The traditional planar source, drain and channel are flat. The gate sits on top of it.
The FinFET turns that planar source, drain and channel onto its side, causing it to rise up above its surrounding area and giving it that 3-D shark fin look for its name. The gate is then wrapped around the top and sides of the channel rather than just sitting on top of it.
The FinFET's primary benefit is that it allows the gate to wrap around the channel on three sides. By contrast, the gate on the old planar transistor covers the channel at just one side.
Furthermore, the FinFET also has a smaller physical footprint. Which means we can continue stuffing more of them onto the same piece of real estate.
The idea is definitely not new. Two conceptually similar proposals were made before, though none of those ideas were ever implemented or turned into a real invention.
The first came from D. Hisamoto, a researcher at Hitachi. Back in 1990, he proposed the idea of wrapping the gate around the channel and making a 3D transistor. His paper called it "a Fully Depleted Lean-Channel Transistor" or DELTA.
Hisamoto in turn was inspired by a paper published by Texas Instruments back in the 1980s calling for a "trench transistor".
The concept is useless without the execution and nobody knew if these transistors can scale to the 25 nanometer world or smaller. Thus with DARPA's financial backing, Hu and his team spent four years prototyping a working FinFET device.
Critically, the team had the freedom to pursue this long term goal, but also with the ability to draw on unusual resources in both the private and public sector. This includes equipment and facilities at Stanford and the Lawrence Berkeley National Lab.
In 2001, the DARPA project ran its course and Hu's team published their results. People quickly realized that the FinFET was a tremendously innovative technology.
But just as critically, the FinFET was not TOO disruptive. The team made sure that traditional lithographic and etching tools can still be used to make it.
This way, the semiconductor industry can get the better performance and power efficiency it wanted without needing to abandon billions of dollars of equipment and decades of experience.
Even so, the semiconductor industry is a conservative one. They did not immediately adopt the FinFET after its publication, instead opting for short-term measures to stave off the MOSFET's last day.
For the 90 to 45 nanometer nodes in the early 2000s, the industry employed strain or stress-based engineering. This is where you add layers of "strained" silicon to the channel - usually on top of a silicon-germanium buffer layer.
Strained, meaning that the silicon's layers of crystal atoms are being stretched. This helps improve the electrons travel faster as they cross the channel. It was also not easy to do, requiring engineers to grow these layers of strained silicon using epitaxy.
High-K Metal Gate
Then at the 28 nanometer process node in 2009-2010, Intel and its cohorts implemented a new type of gate into its transistors. This was called a High-K Metal Gate.
Remember me earlier mentioning that there was an insulating layer of silicon dioxide between the gate and the channel?
With the High-K metal gate, we replace that layer of silicon dioxide with one made from a high-K metal like hafnium oxide. This High-K - high in relation to traditional silicon dioxide - keeps the opposing charges apart from each other where they belong.
This concept was also not easy to pull off. It led to the infamous "Gate First or Gate Last" dilemma that split the industry and caused a whole raft of semiconductor manufacturers to drop off the leading edge.
I talked about that in more detail in my video about UMC.
Unfortunately, the benefit that High-K metal gates give us is one-time only. So for the next node after 28 nanometers, the foundries needed a new rabbit to pull out of the hat. It was time to go 3D
For its next big node after 28 nanometers - 22 nanometers - Intel chose to implement a 3-D device which they called the Tri-Gate transistor.
The Tri-Gate is a descendant of the original FinFET. That original device had two gates on each of the two sidewalls around the fin. Referred to as a Double-Gate FinFET.
Over time, the industry found that these options won't yield. They modified it to create what Intel eventually shipped - three gate layers on all of the fin's three exposed sides.
Ergo, the Tri-Gate adjective. Most people refer to them as FinFETs anyway as will I.
Going from prototype to mass production is always challenging.
The fin's geometry - width, height, etc - as well as the spacing between the fins - called the fin pitch - play a big role in its overall performance. These are extremely small. At the 20 nanometer process node or smaller, the fin is just 10 nanometers wide.
The fin pitch is about 60 nanometers. Millions of these nano-scale fins have to be fabricated with extremely little variation.
Coming at the same time as a bunch of new multi-patterning techniques, this was extremely difficult. After Intel, all of the foundries struggled with scaling their first FinFET products with yield, resulting in delays.
TSMC and Samsung finally made the jump in 2013 with what they named their 16/14 nanometer processes.
GlobalFoundries joined with their own 14 nanometer process in 2014. They licensed their process from Samsung.
Gate All Around
FinFETs did well through the N7 and N5 generations. But recently those too are losing their effectiveness.
Foundries are doing all they can to squeeze more performance - for instance, making the fins increasingly taller - but eventually a new set of architectures is required. The industry has decided upon Gate all around as that new architecture.
The FinFET worked better because its gate covered more surface area on the channel for better control.
Gate all around takes this idea further by completely surrounding the channel, even from the bottom where it was not before.
Completely wrapping the gate around the channel also means that we can stack multiple channels - or nanowires - on top of each other as they pass through the gate. Pretty nifty.
In June 2022, Samsung started shipping its 3 nanometer process with the Gate-All-Around FET.
TSMC is sticking with FinFETs for their upcoming N3 process node. But they will adopt Gate-all-around for their next big node step, N2 - which is under construction over in Baoshan.
These 3D transistors are a technical marvel. But they do not come cheap.
The added cost of the FinFET’s intricate construction means that 28 nanometers - the last with planar gates - is the point at which the cost per gate stops declining and starts rising again.
Gate all around accelerates that trend even further. How do you build out the gaps between the nanowires when you can only etch in a downwards direction? The solution involves superlattices and a new methodology called atomic layer deposition. I will save it for later.
These new structures make the leading edge even more economically infeasible for all but the biggest companies. And perhaps not even them.
In a recent interview, ASML's CTO says that he thinks we are reaching the end of lithography. Not because of technology, but because of economic feasibility.
We can always come up with the next structure. The next FinFET. The next Gate all around. The next EUV. But who or what next can be able to pay for it? That's the biggest question of all.